I understand what it means to reach the memory that it is a coalition, but I do not understand why this Necessary. For example, how can I use a byte from an address 0x ... 1 but I can not use one half word (two bytes) from the same address.
Again, I understand that if you have an address of A and s , then the entry is aligned if A mod S = 0 . But I do not understand why it is important at the hardware level.
The hardware is complex; This is a simple explanation.
A typical modern computer may have a 32-bit data bus, which means that any fitch that needs to be done will receive a special memory address for all 32 bits . Since the data can not just fetch anything less than 32 bits, so at least two address bits are not used on the address bus, so it seems that the 32-bit words < / Em> instead of 8-bit bytes .
When the CPU does one fetch for a byte, then the reading cycle will bring 32 bits and then the CPU will end 24. Those bits, the remaining 8 bits which are loaded in the register If the CPU wants to get 32 bit value which is a not alliance on the 32-bit limit, then there are several common options in it:
Two separate reading Execute chakras with just loading the appropriate parts of the word word and Read something Throw out an exception Read the 32-bit word at the address specified by throwing at least two bits of the address < / Li> I have worked with several CPUs, which have taken four out of four, usually those paths, for maximum compatibility it all aligns the N-bit to read in the N-bit range Is the safest. However, you can definitely take shortcuts if you are sure that your software will run with a specially identifiable behavior known to the CPU family. And if untrained reading is also possible (such as x86 family on CPU), then they will be slow
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