VHDL How to add a std_logic_vector with a std_logic signal together? -

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मुझे मिला है 

  douta: std_logic_vector (3 downto 0); Doutb: std_logic_vector (3 से डाउन 0); C0: std_logic में; F1: std_logic में; F0: std_logic में; Res: बाहर std_logic_vector (3 डाउन डाउन 0);

मैं एक साधारण एएलयू बनाने का प्रयास कर रहा हूं, और यह एएलयू प्रदान करता है फ़ंक्शन में से एक है जब 

  f1 और f0 both = 1 res = douta प्लस बी प्लस सी 0

तो मैंने लिखा 

  f1 = '1' और f0 = '1' फिर res & lt; = douta + doutb + c0;

लेकिन जाहिर है यह काम नहीं करने वाला है क्योंकि douta और doutb का डेटाटाइप है std_logic_vector जहां के रूप में < कोड> सह बस std_logic

और मुझे संकलन करते समय यह त्रुटि मिली 

  'त्रुटि 603 लाइन 34: असंगत प्रकार के लिए अंकगणित ऑपरेटर: एलएचएस = std_logic_vector! 18, आरएचएस = std_logic

कोई समस्या है कि मैं इस समस्या को ठीक कैसे कर सकता हूं?

संपादित करें: कोशिश की 

  f1 = '1' और f0 = '1' फिर res & lt; = douta + doutb + ("000" & amp; c0);

लेकिन अभी भी कोई भाग्य नहीं है, इस बार संकलक कहता है 

  LHS = std_logic_vector! 7, आरएचएस = array_1_of_std_logic_3_d_0

कृपया std_logic_vector का उपयोग न करें, अगर आप उन पर अंकगणित करने जा रहे हैं। ieee.numeric_std का उपयोग करें, और हस्ताक्षरित या हस्ताक्षरित प्रकारों का उपयोग करें। इसके बाद आप इसे '0' या '1' में जोड़ सकते हैं।

std_logic_arith.all का उपयोग करने का हल एक गैर-मानक पुस्तकालय का उपयोग कर एक निराशा है, जो प्राप्त हो सकता है जब आप टूलचें बदलते हैं तो पोर्टेबिलिटी मुसीबतों में।

मैंने इसके बारे में और अधिक विस्तृत पृष्ठ लिखा:

इस पर comp.lang.vhdl पर कुछ चर्चा हुई थी: और भी Comp.lang.vhdl FAQ।


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